Exercise 6

Objective

Consolidate RISC-V assembly learning and understand how conditional branch instructions are executed inside a loop. The following C expression is translated into assembly using slti and beq:

for (i = 0; i < 3; i++)
    j++;

Instructions

Open the RISC-V simulator.
Transcribe the code below into the editor:

# Exercise 06
# C expression: for (i = 0; i < 3; i++) j++;

    .text
main:
    addi s0, zero, 0     # i = 0

Loop:
    slti t0, s0, 3       # if i < 3 then t0 = 1, else t0 = 0
    beq  t0, zero, Exit  # if t0 == 0, jump to Exit
    addi s1, s1, 1       # j++
    addi s0, s0, 1       # i++
    j    Loop            # go back to Loop

Exit:
    nop                  # end of program

Step-by-step Execution

Run the program step by step using the Run One Step button. For each instruction, fill in the table below whenever a register is modified.

Fill in the table below

Fill in the PC with the instruction address and copy the Instruction column exactly as it appears in the simulator. Only fill in fields that are modified.
For pseudo-instructions, the simulator shows the real instruction in the Basic column and the original form in the Source column. Copy the Basic value into the Instruction column and the Source value into the Pseudo-instruction column. Leave the pseudo column blank for non-pseudo instructions.
If you need more rows, click Add row. Verification only runs when all rows are filled, if nothing appears after clicking Check, it means there are still empty rows.

Before			After executing the instruction
PC	Instruction	Pseudo-instruction	x5	x8	x9
			(t0)	(s0 (i))	(s1 (j))
			0x00000000	0x00000000	0x00000000
0x00400000	addi s0 zero 0			0x00000000

Tip: in the print dialog, select A2 paper size for best results.